An AI agent designed a complete RISC-V CPU core from a 219-word specification in 12 hours. The system, called Design Conductor, was built by chip design startup Verkor.io, and the resulting processor, dubbed VerCore, went from a short requirements document to a verified, layout-ready GDSII file without human intervention during the actual design process. A research paper published in March 2026 backs the claim.
What "designed" actually means here
The headline deserves careful parsing. Design Conductor is not itself an AI model; it is a harness that constrains large language models to follow a set of instructions toward a defined objective. Like human engineers, it followed the conventional design cycle of design, build, test and refine, but did so on its own instead of relying on separate automation tools for each stage.
VerCore is a five-stage pipeline, in-order, single-issue architecture running at 1.48 GHz, and it scored 3,261 on CoreMark, a standard microcontroller benchmark. That puts it roughly in the tier of an entry-level Intel Celeron SU2300 from mid-2011. It is unlikely to compete with any modern CPU. It has not been physically fabricated; it was validated in the Spike reference RISC-V simulator, and its layout used ASAP7, an open-source academic process design kit developed at Arizona State University in collaboration with ARM Research, not a production 7nm node. Verkor says it can run a uCLinux variant in simulation.
Verkor's own paper is candid about the limits. The agent sometimes underestimates the complexity of the work required: when failing timing, it tried to deepen the pipeline instead of looking for simpler explanations, and it reasoned about Verilog, an event-driven language, as if it were sequential code, which made timing bugs harder to debug. The researchers estimate five to ten human experts would still be needed to steer the system toward a production-ready chip, and the 219-word spec was engineered input, not a casual prompt. Verkor has said it will release the RTL source and build scripts, and demonstrate an FPGA implementation.
The milestone table
VerCore is not the first AI-designed CPU, but it is the first claimed end-to-end agentic design from spec to GDSII. Verified milestones:
| When | Who | What | Time | Performance | Fabricated? |
|---|---|---|---|---|---|
| 2023 | Chinese Academy research team | Industrial-scale RISC-V CPU, fully automated design | Under 5 hours | About i486-class | No (paper design) |
| March 2026 | Verkor.io (Design Conductor) | Complete VerCore RISC-V core, spec to GDSII with zero intervention during design | 12 hours | CoreMark 3,261 (2011 Celeron tier) | No (simulation only) |
Hardware vs cryptography: the other AI breakthrough this week
The comparison that puts VerCore in context is GPT-6 Astra cracking a 217-year-old Napoleonic cipher in 6 hours, which we covered this week. The two stories are mirror images of the same capability: agents doing engineering work. The cipher run was about reasoning and pattern extraction; the CPU run was about orchestrating a multi-stage toolchain (RTL generation, synthesis, timing closure) that humans take 18 to 36 months to walk. Notably, the agent's own paper admits the process consumed many tens of billions of tokens for a comparatively simple design, with compute requirements growing non-linearly as complexity rises. That token bill is the real bottleneck, and it is exactly what our scorecard of five AI coding assistants measured on the software side: agentic engineering is real, but it is expensive per unit of output.
The honest takeaway
VerCore will not threaten commercial chip design this year. But it moves the goalpost: in 2023 an AI could design an i486-class chip in five hours with heavy constraints; in 2026 an agentic harness claims to have run the whole flow itself and landed at 2011-level performance in twelve. The trajectory is clear even if the destination is far. If the FPGA demo and RTL release materialize as promised, the industry gets something more valuable than a headline: a reproducible artifact to argue about.
By ByteHerald Staff. Technical details from Verkor's March 2026 paper via Tom's Hardware and TechSpot reporting; 2023 milestone from the Chinese Academy paper via Tom's Hardware.
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